English: A table showing a data hazard in the pipelined execution of instructions in a microprocessor. In this case, the instructionas are something like the following:

SUB r3,r4 -> r10
AND r10,3 -> r11

In this case in a naive pipeline, r10 will be used in the EXECUTE step (red) by the AND before the SUB operation performs WRITEBACK on it (green).